The continued size reduction of metal-oxide-semiconductor field-effect transistors (MOSFET) has improved the speed, density, and cost per unit function of integrated circuits. One way to increase MOSFET performance is through selective application of stress to the transistor channel region. Stress distorts or strains the semiconductor crystal lattice, which affects the band alignment and charge transport properties of the semiconductor. By controlling the magnitude and distribution of stress in a finished device, manufacturers can increase carrier mobility and improve device performance. There are several existing approaches of introducing stress in the transistor channel region.
In one conventional approach, a strained-channel transistor is fabricated on an epitaxial Si layer that is grown on a relaxed SiGe layer. Because the lattice constant of SiGe is larger than Si, the epitaxial Si layer is under a biaxial tensile strain. A transistor made on the epitaxial strained-Si layer will have a channel region under the biaxial tensile strain. In this approach, relaxed SiGe layer serves as a stressor that introduces strain in the channel region. In another approach, a high-stress film is formed over a completed transistor. The high-stress film distorts the silicon lattice thereby straining the channel region.
In another approach, for example in PMOS fabrication, a method uses substrate structures that apply a compression stress to the channel. One method uses modified shallow trench isolation (STI) structures that compress the PMOS channel. Another method forms an embedded SiGe layer within the source/drain regions for compressing the PMOS channel.
In a conventional process, the embedded SiGe stressor is formed using selective epitaxy growth (SEG), chemical vapor deposition, ultra-high vacuum chemical vapor deposition, or molecular beam epitaxy. These approaches are very expensive because a several micron thick SiGe layer is often used. Also, numerous dislocations exist within the SiGe layer, some of which propagate to strained-Si layer, resulting in high defect density, thereby negatively affecting transistor performance. Other problems include complicated process integration and low throughput.
In light of these problems, workers in the art have developed advanced implantation methods for SiGe stressor formation. One method uses gas cluster ion beam (GCIB) irradiation. J. O. Borland, et al. in U.S. Patent Application Publication No. US 2005/0181621 A1, which publication is hereby incorporated by reference in its entirety, provides the details of an infusion process. Unlike conventional ion implantation, which involves individual ions, the GCIB process implants clusters of atoms. Infusion therefore enables simultaneous implantation of multiple chemical species. Infusion also enables more rapid and economical implantation of concentrated dopants, such as SiGe alloys used in strained transistor engineering.
Despite recent advances in strain engineering, problems remain. Infusion generates end of range (EOR) defects in the substrate. EOR defects enhance migration of dopants and stressors thereby making steep concentration gradients near stressors and abrupt junctions difficult to form. Annealing removes some EOR defects, but requires additional process steps, and it is not completely effective. Accordingly, there still remains a need for improved structures and methods for strain engineered semiconductor device fabrication.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate certain embodiments, a letter indicating variations of the same structure, material, or process step may follow a figure number.